In recent years, various types of the semiconductor devices in which a plurality of memory chips are stacked on a wiring board have been developed in order to achieve an increased capacity of a semiconductor memory and reduction in size of the semiconductor device.
Japanese Patent Application Laid-Open Publication No. 2006-351664 (patent document 1) has disclosed a system in package (SIP) in which a plurality of memory chips and a microcomputer chip are stacked on a wiring board. In this SIP, a plurality of memory chips and a microcomputer chip are stacked on a surface of a wiring board and an interposer chip composed of a silicon substrate is disposed on a surface of the memory chip adjacently to the microcomputer chip. Also, pads of the microcomputer chip are connected to pads of the wiring board through the interposer chip and bonding wires.
Japanese Patent Application Laid-Open Publication No. 2002-33442 (patent document 2), Japanese Patent Application Laid-Open Publication No. 2002-217356 (patent document 3) and Japanese Patent Application Laid-Open Publication No. 2007-59541 (patent document 4) have disclosed a semiconductor device in which semiconductor chips each having a plurality of bonding pads formed on one side thereof are stacked on a wiring board. The respective semiconductor chips are disposed so that their sides having the bonding pads formed thereon are directed in opposite directions to each other, and are stacked in a dislocated manner alternately in a direction perpendicular to the sides.
Japanese Patent Application Laid-Open Publication No. 2006-86149 (patent document 5) has disclosed a semiconductor device having a stacked multi-chip package structure in which a plurality of semiconductor chips and a rewiring element (interposer) are stacked and mounted on a wiring board. The rewiring element has wirings for connecting between the plurality of semiconductor chips and between the wiring board and the semiconductor chips, and mutual connection between the plurality of semiconductor chips and rearrangement of the pads of the semiconductor chips are achieved with the rewiring element.
Japanese Patent Application Laid-Open Publication No. 2005-244143 (patent document 6) has disclosed a semiconductor device in which an interface chip is stacked on a plurality of stacked semiconductor chips. A Si interposer and a resin interposer are disposed below the plurality of semiconductor chips. The Si interposer is disposed between the resin interposer and the plurality of semiconductor chips, has a thickness larger than that of the semiconductor chip, and has a linear expansion coefficient smaller than that of the resin interposer and larger than that of the plurality of semiconductor chips.
Japanese Patent Application Laid-Open Publication No. 2007-66922 (patent document 7) has disclosed a semiconductor integrated circuit device having a stacked structure package. This semiconductor integrated circuit device has a stacked structure in which a plurality of semiconductor chips are stacked on a printed wiring board, and a semiconductor chip mounted on the lowermost portion is provided with an interface circuit. This interface circuit includes a buffer, an electrostatic protection circuit and others, and signals to be input or output into/from the plurality of semiconductor chips are all input or output through this interface circuit.
Japanese Patent Application Laid-Open Publication No. 2007-128953 (patent document 8) has disclosed a semiconductor device in which first and second semiconductor chips each having a pad structure formed on one long side thereof are stacked and mounted on a wiring board having connecting pads. The second semiconductor chip is smaller than the first semiconductor chip and has a narrow shape. The first and second semiconductor chips are electrically connected to the connecting pads of the wiring board 2 through bonding wires, and the second semiconductor chip is disposed so that the long side L is parallel to an ultrasonic wave application direction X at the time of wire bonding.
Japanese Patent Application Laid-Open Publication No. 2007-96071 (patent document 9) has disclosed a semiconductor memory card which can mount a large-capacity nonvolatile memory chip. This semiconductor memory card includes: a rectangular circuit board; a rectangular nonvolatile memory chip which is mounted on the circuit board and has a plurality of first bonding pads formed along only a first side thereof, the first bonding pads being wire-bonded to a plurality of first board terminals formed in the proximity of the first side; and a rectangular controller chip which is mounted on the nonvolatile memory chip so that the direction of a second side of the nonvolatile memory chip adjacent to the first side is substantially parallel to the direction of a long side of the rectangular controller chip and has a plurality of second bonding pads formed along the direction of the long side thereof, the second bonding pads being wire-bonded to a plurality of second board terminals formed on the circuit board in the proximity of the long side of the rectangular controller chip.
Japanese Patent Application Laid-Open Publication No. 2004-63579 (patent document 10) has disclosed a semiconductor device in which two semiconductor chips each having bonding pads formed on their two sides perpendicular to each other are stacked. The second semiconductor chip stacked on the first semiconductor chip is mounted in a dislocated manner in X and Y directions so that the bonding pads on the two sides of the first semiconductor chip are exposed.
Japanese Patent Application Laid-Open Publication No 2005-339496 (patent document 11) has disclosed a multi-function memory card in which a plurality of flash memory chips are stacked and mounted on a main surface of a wiring board and a controller chip and an IC card microcomputer chip as a security controller are mounted on the flash memory chip of the uppermost layer. In each of the plurality of flash memory chips, bonding pads are formed on one short side thereof, and the flash memory chips are stacked in a dislocated manner by a predetermined distance in a long side direction so that the bonding pads are exposed.